The present invention relates generally to integrated circuit designs, and, more particularly, to word-line driver designs.
The core of a semiconductor memory comprises at least one two-dimensional memory cell array, where information is stored. Traditionally, word-lines select rows which activate cells and bit-lines select columns, which access, i.e., read or write, cells. When a word line and a bit line are activated, a particular memory cell connected to them is selected.
As memory density increases, the number of word-line drivers or the number of memory cells on a single word-line will increase, in either case, the total size of the word-line driver will increase. Large word-line driver size contributes to a large amount of leakage. In fact, in a static random access memory (SRAM), word-line driver leakage normally contributes to more than half of the total leakage of a SRAM chip.
The number of word-line drivers will even double in two-port SRAMs, as read and write employs separate word-lines. This not only increases a chips' leakage, but also occupies a large chip area. In a pseudo two-port register file case, where speed is less critical, concurrent read and write can be realized by writing after reading a cell in one cycle. Then only one word-line is needed and hence the memory cells can be traditional 6-T SRAM cells.
As such, what is needed is a word-line driver design that can assert a word-line for either read or write operation in the pseudo two-port register file.